Higher integration and higher functionality of semiconductor devices have been progressing in the form of miniaturization of pattern dimensions, but in recent years, new structures have emerged. Particularly in logic devices, transistors of a three-dimensional structure called fin field effect transistors (FinFETs) are becoming mainstream from the planar type. As illustrated in FIG. 1, a typical structure of a FinFET has a shape in which a gate pattern 110 orthogonal to a fin is overlaid on a line pattern 120 called a fin (Fin). Note that FIG. 1 depicts these elements in a birds-eye view so as to illustrate the relationship between the fins and the gates. Although only one fin and one gate are illustrated in the drawing, a plurality of fins and gates are formed in parallel in many cases.
To avoid confusion, fins and gates are usually line patterns and X, Y, and Z axes are defined as illustrated in FIG. 1. The Z region under the convex portion of the fin is divided into three regions, as illustrated in FIG. 1, that is, a substrate 100, a first layer 140 in which the fin is located, and a second region 130 in which the gate on the fin is located. The fin is indicated as a first line 120. In addition to the fin, the first layer 140 includes a gate pattern divided by the fin. Further, the gate pattern (which is present across both the first and second layers) is referred to as a second line 110. Reference numeral 121 denotes a region between the fins.
In the semiconductor device, a gate length, that is, a width of the second line 110 corresponding to the gate in the portion in contact with the fin is an important performance index. To obtain the gate length, the line width of the gate in contact with the fin in the first layer and the line width of the gate in contact with the fin at the boundary between the first layer and the second layer are needed.
Nondestructive high throughput is important in inspections in conventional semiconductor processes, and a top-down electron microscope that can load wafers as they are is used. In particular, those having a stable measurement function are called critical dimension scanning electron microscopes (CD-SEMs). In the case of the conventional planar transistor, the outline corresponding to the left and right edges of the gate line is extracted from the CD-SEM observation image of the gate pattern and the average line width (gate size), line-edge roughness (LER), and local line width fluctuation (linewidth roughness, LWR) are calculated and used as indices of the quality of the pattern and the process is managed.
Although it is desirable to use this CD-SEM also in management in the manufacturing process of FinFET, it is difficult to accurately measure the gate length since the portion where the gate line is in contact with the fin surface is located behind the intricate structure as seen from above. However, extracting and monitoring the index value corresponding to the gate quality from the top-down observation image is effective as an alternative method of true gate length measurement. In the case of the inspection of the gate of the FinFET, the average gate size, the difference in the gate dimensions of the portion where the fin exists (hereinafter referred to as On-Fin) and the portion without the fin (also called Off-Fin) and a roughness index of the gate line (LER or LWR) are examples of indices for process management. In short, it is effective to precisely extract these three indices from the top-down CD-SEM image and use the extracted indices as an index of pattern quality in inspection after gate processing to reduce defects in FinFETs.
To calculate these indices, it is necessary to obtain the dimensions of the gate in both the On-Fin and Off-Fin regions, and for that purpose, it is necessary to extract the outline of the pattern. PTL 1 is one example of a top-down observation image evaluation method of a pattern overlapping different lower layers.
Although the outline of the figure is a continuous curve, the outline actually taken out from the image is a polygonal line, so that the information of position coordinates of the discrete edge points is obtained. Hereinafter, the position coordinates of the discrete edge points are referred to as an edge. A typical method for extracting the edge of a line pattern in the image from the scanning electron microscopic image (i.e., a method used in measuring the gate pattern dimensions of the planar transistor) is described.
For convenience, assume that the X and Y coordinates are set in the image and the gate line runs in the vertical direction (Y direction). For such an image, the X direction distribution of luminance with fixed Y is defined as a signal profile. X coordinates of a fixed intensity on the signal profile is often regarded as the edge. However, the image may have a gentle luminance distribution in the vertical direction. For example, there is a case where the Y coordinate is larger for the brighter signal. Upper and lower ends may become dark. Even in such a case, to detect an appropriate edge position, a threshold method has been widespread, in which the points that internally divide the interval between the minimum value of the signal or the average value of the dark portion called baseline (hereinafter these two values are referred to as the base intensity) and the maximum value at a fixed ratio are regarded as the edge. In some cases, a method of defining a point where the slope of the signal profile becomes steepest as an edge may be used. This method is called a slope method herein.